`timescale 10fs/1fs
module TEST_Memory;
	reg iClk, iMemRead, iMemWrite;
	reg [31:0] iAddress, iWriteData;
	wire [31:0] oMemData;

	Memory U0(.*);
	
	initial begin
		#0 iClk <=1'b0;
		forever #0.5 iClk<=~iClk;
	end
	
	initial fork
	#0 {iMemRead, iMemWrite}<=2'b01;
	#0 iAddress <= 32'b0;
	#0 iWriteData <= 32'b10;
	#1 iAddress <= 32'b1;
	#1 iWriteData <= 32'b110;
	#2 iAddress <= 32'b1001;
	#2 iWriteData <= 32'b1010;
	
	#5 {iMemRead, iMemWrite}<=2'b10;
	#5 iAddress <= 32'b0;
	#6 iAddress <= 32'b1;
	#7 iAddress <= 32'b1001;
	
	
	join

endmodule